The existing CMOS technology is reaching its limits beyond which the down-scaling in feature size and proper working of the device is becoming extremely difficult. CMOS devices suffer from heat generation as they have to discharge all the stored energy when flipping from 1 to 0. Quantum dot cellular automata (QCA) is one of the emerging nanotechnologies in which it is possible to achieve circuit densities and clock frequencies much beyond the limit of existing CMOS technology. QCA has significant advantages in terms of power dissipation as it does not have to dissipate all its signal energy hence the reason it is considered as one of the promising technologies to achieve the thermodynamic limit of computation.
QCA attempts to create general computational functionality at the nanoscale by controlling the position of single electrons. The fundamental unit of QCA is the QCA cell, or set of cells each of which is comprised of several quantum dots. FIG. 1A shows a cell 100 created with four quantum dots 105 positioned at the vertices of a square. The bounding box shown around the cell 100 is used only to identify one cell from another and does not represent any physical system. Two of the quantum dots 105 are electron containing dots 110.
These QCA cells can be controlled by clock signals to ignore their environment when relaxing or in a relaxed state, to respond to their environment when they are in the process of locking into a state, and to be independent of their environment, and maintain a given state when they are in a locked state that prevents quantum tunneling. When the cells are responding to their environment, they tend to align in one of two directions, as shown in FIG. 1A and FIG. 1B, and this bistable behavior can be used to encode a binary signal by assigning a “0” to one of the states, such as the state shown in FIG. 1A and a “1” to the other state, as shown in FIG. 1B. A cell also tends to align in the same direction as those cells surrounding it.
There are fourth basic QCA logic devices, which are shown in FIGS. 2 through 5. FIG. 2 shows a majority voter (MV) which takes three inputs A, B, and C and determines a logical majority according to the equation F=AB+AC+BC. FIG. 3 shows an inverter (INV), which inverts input A to give an output F=A′. FIG. 4 shows a binary wire and FIG. 5 shows an inverter chain.
The Launder four-phase clocking scheme is generally used in QCA design. Due to significant error rates in nano-scale manufacturing, nanotechnologies including QCA require an extremely low device error rate. In manufacturing QCA, defects can occur in the synthesis and deposition phases. However, defects are more likely to take place during the deposition phase. Researchers assume that QCA cells have no manufacturing defects and, in metal, QCA faults occur due to cell misplacement. These defects can be characterized as cell displacement, cell misalignment, and cell omission. Researchers have proved that molecular QCA cells are more susceptible to missing/additional QCA cell defects. Additional cell defect is due to the deposition of an additional cell on the substrate while missing cell defect is due to loss of a particular cell. QCA devices are also prone to transient faults caused by thermodynamic effects, radiation, and other effects, as the energy difference between the ground and the excited state is small. Thus, researchers have used novel concepts, such as reversible logic, to improve the testability of molecular QCA.
The testing of QCA was addressed for the first time in a seminal work by M. B. Tahoori et al. M. B. Tahoori, J. Huang, M. Momenzadeh, and F. Lombardi, “Testing of Quantum Cellular Automata,” IEEE Trans. Nanotechnol., vol. 3, no. 4, pp. 432-442, December 2004. In Tahoori et al., the defect characterization of QCA devices is investigated and is shown how the testing of QCA differs from conventional CMOS. In M. Momenzadeh et al., the modeling of QCA defects at molecular level is done for combinational circuits. M. Momenzadeh, M. Ottavi, F. Lombardi, “Modeling QCA defects at molecular level in combinational circuits”, Proc. DFT in VLSI Systems, Monterey, Calif., USA, 3-5 October 2005, pp. 208-216. Fault characterization is done for single missing/additional cell defect on different QCA devices such as MV, INV, fan-out, crosswire and L-shape wire. In P. Gupta, et al., test generation framework for QCA is presented. P. Gupta, N. K. Jha, L. Lingappan, “A Test Generation Framework for Quantum Cellular Automata Circuits”, IEEE Trans. VLSI Syst., Vol. 15, no. 1, pp. 24-36 (January 2007). It is seen that additional test vectors can be generated for detecting QCA defects, which remain undetected by stuck-at fault model. Bridging fault on QCA wires is also addressed. In X. Ma et al., reversible logic is used to detect single missing/additional cell defects. X. Ma, J. Huang, C. Metra, F. Lombardi, “Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA”, Springer Journal of Electronic Testing, vol. 24, no. 1-3, pp. 297-311 (June, 2008). It is seen that reversible one-dimensional array is C-testable. In T. Wei et al., fault-tolerant QCA designs are presented using triple modular redundancy with shifted operands. The strategy is proposed considering the wire delay and faults in wires in QCA. T. Wei, K. Wu, R. Karri, and A. Orailoglu, “Fault Tolerant Quantum Cellular Array (QCA) Design Using Triple Modular Redundancy with Shifted Operands”, Proc. ASPDAC 2005, Shanghai, China, pp. 1192-1195 (January 2005).
There is an existing popular conservative gate called the Fredkin gate. A block diagram of the Fredkin gate is shown in FIG. 6. The Fredkin gate can be described as mapping (A, B, C) to (P=A, Q=A′B+AC, R=AB+A′C), where A, B, C are input and P, Q, R are output, respectively. The Fredkin gate produces the same number of ones (1's) on the output as were put on the input.
The QCA design of the Fredkin gate is shown in the circuit diagram of FIG. 7. The Fredkin gate has a two-level majority voter (MV) implementation and it requires six majority voters (majority gates). As shown in FIG. 7, the Fredkin gate also requires two inverters and has a four-phase clocking scheme. Inputs A, B, and C are taken into the circuit at clock zone zero (D0), the first set of majority voters are in clock zone one (D1), the outputs of the first set of majority voters are in clock zone two (D2), and the second set of majority voter are in clock zone three (D3). The QCA layout of the Fredkin gate is shown in FIG. 8.